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Macros</h2></td></tr>
<tr class="memitem:ga483f73470c465c0ce9317a14c4546130"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga483f73470c465c0ce9317a14c4546130">XSCUWDT_HW_H</a></td></tr>
<tr class="memdesc:ga483f73470c465c0ce9317a14c4546130"><td class="mdescLeft">&#160;</td><td class="mdescRight">&lt; prevent circular inclusions  <a href="group___overview.html#ga483f73470c465c0ce9317a14c4546130">More...</a><br/></td></tr>
<tr class="separator:ga483f73470c465c0ce9317a14c4546130"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0c00c40fbb11db997a4650ae222ac29f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga0c00c40fbb11db997a4650ae222ac29f">XScuWdt_ReadReg</a>(BaseAddr, RegOffset)&#160;&#160;&#160;Xil_In32((BaseAddr) + ((u32)RegOffset))</td></tr>
<tr class="memdesc:ga0c00c40fbb11db997a4650ae222ac29f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read the given register.  <a href="group___overview.html#ga0c00c40fbb11db997a4650ae222ac29f">More...</a><br/></td></tr>
<tr class="separator:ga0c00c40fbb11db997a4650ae222ac29f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga396641b45a7213c8c18a19485759fee4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga396641b45a7213c8c18a19485759fee4">XScuWdt_WriteReg</a>(BaseAddr, RegOffset, Data)&#160;&#160;&#160;Xil_Out32((BaseAddr) + ((u32)RegOffset), ((u32)Data))</td></tr>
<tr class="memdesc:ga396641b45a7213c8c18a19485759fee4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Write the given register.  <a href="group___overview.html#ga396641b45a7213c8c18a19485759fee4">More...</a><br/></td></tr>
<tr class="separator:ga396641b45a7213c8c18a19485759fee4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Register Map</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Offsets of registers from the start of the device.</p>
<p>The WDT registers start at an offset 0x20 </p>
</div></td></tr>
<tr class="memitem:ga0ed3512c06a5468c1a1e156485c89b05"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga0ed3512c06a5468c1a1e156485c89b05">XSCUWDT_LOAD_OFFSET</a>&#160;&#160;&#160;0x00U</td></tr>
<tr class="memdesc:ga0ed3512c06a5468c1a1e156485c89b05"><td class="mdescLeft">&#160;</td><td class="mdescRight">Watchdog Load Register.  <a href="group___overview.html#ga0ed3512c06a5468c1a1e156485c89b05">More...</a><br/></td></tr>
<tr class="separator:ga0ed3512c06a5468c1a1e156485c89b05"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3baeac323b13ac9c8fb14b26ecb1080b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga3baeac323b13ac9c8fb14b26ecb1080b">XSCUWDT_COUNTER_OFFSET</a>&#160;&#160;&#160;0x04U</td></tr>
<tr class="memdesc:ga3baeac323b13ac9c8fb14b26ecb1080b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Watchdog Counter Register.  <a href="group___overview.html#ga3baeac323b13ac9c8fb14b26ecb1080b">More...</a><br/></td></tr>
<tr class="separator:ga3baeac323b13ac9c8fb14b26ecb1080b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabb582c48f399b333543c54e0563809d5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gabb582c48f399b333543c54e0563809d5">XSCUWDT_CONTROL_OFFSET</a>&#160;&#160;&#160;0x08U</td></tr>
<tr class="memdesc:gabb582c48f399b333543c54e0563809d5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Watchdog Control Register.  <a href="group___overview.html#gabb582c48f399b333543c54e0563809d5">More...</a><br/></td></tr>
<tr class="separator:gabb582c48f399b333543c54e0563809d5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga51a62e1dedd6b0f5f45cd19305f09440"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga51a62e1dedd6b0f5f45cd19305f09440">XSCUWDT_ISR_OFFSET</a>&#160;&#160;&#160;0x0CU</td></tr>
<tr class="memdesc:ga51a62e1dedd6b0f5f45cd19305f09440"><td class="mdescLeft">&#160;</td><td class="mdescRight">Watchdog Interrupt Status Register.  <a href="group___overview.html#ga51a62e1dedd6b0f5f45cd19305f09440">More...</a><br/></td></tr>
<tr class="separator:ga51a62e1dedd6b0f5f45cd19305f09440"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga265a4196811ab4b4ac12954d02461520"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga265a4196811ab4b4ac12954d02461520">XSCUWDT_RST_STS_OFFSET</a>&#160;&#160;&#160;0x10U</td></tr>
<tr class="memdesc:ga265a4196811ab4b4ac12954d02461520"><td class="mdescLeft">&#160;</td><td class="mdescRight">Watchdog Reset Status Register.  <a href="group___overview.html#ga265a4196811ab4b4ac12954d02461520">More...</a><br/></td></tr>
<tr class="separator:ga265a4196811ab4b4ac12954d02461520"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8322daafd0ea0ea44c59f69523b19f66"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga8322daafd0ea0ea44c59f69523b19f66">XSCUWDT_DISABLE_OFFSET</a>&#160;&#160;&#160;0x14U</td></tr>
<tr class="memdesc:ga8322daafd0ea0ea44c59f69523b19f66"><td class="mdescLeft">&#160;</td><td class="mdescRight">Watchdog Disable Register.  <a href="group___overview.html#ga8322daafd0ea0ea44c59f69523b19f66">More...</a><br/></td></tr>
<tr class="separator:ga8322daafd0ea0ea44c59f69523b19f66"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Watchdog Control register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register bits control the prescaler, WD/Timer mode, Intr enable, auto-reload, watchdog enable. </p>
</div></td></tr>
<tr class="memitem:gae0774dc548157f183fa5c365fcc8f251"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gae0774dc548157f183fa5c365fcc8f251">XSCUWDT_CONTROL_PRESCALER_MASK</a>&#160;&#160;&#160;0x0000FF00U</td></tr>
<tr class="memdesc:gae0774dc548157f183fa5c365fcc8f251"><td class="mdescLeft">&#160;</td><td class="mdescRight">Prescaler.  <a href="group___overview.html#gae0774dc548157f183fa5c365fcc8f251">More...</a><br/></td></tr>
<tr class="separator:gae0774dc548157f183fa5c365fcc8f251"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac19052eae87df391ecfc92476c6be092"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gac19052eae87df391ecfc92476c6be092"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSCUWDT_CONTROL_PRESCALER_SHIFT</b>&#160;&#160;&#160;8U</td></tr>
<tr class="separator:gac19052eae87df391ecfc92476c6be092"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7c5148db8727a2fdbab1c7dba9296f77"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga7c5148db8727a2fdbab1c7dba9296f77">XSCUWDT_CONTROL_WD_MODE_MASK</a>&#160;&#160;&#160;0x00000008U</td></tr>
<tr class="memdesc:ga7c5148db8727a2fdbab1c7dba9296f77"><td class="mdescLeft">&#160;</td><td class="mdescRight">Watchdog/Timer mode.  <a href="group___overview.html#ga7c5148db8727a2fdbab1c7dba9296f77">More...</a><br/></td></tr>
<tr class="separator:ga7c5148db8727a2fdbab1c7dba9296f77"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga88489f11e8c766bd4ba2c725087b16fc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga88489f11e8c766bd4ba2c725087b16fc">XSCUWDT_CONTROL_IT_ENABLE_MASK</a>&#160;&#160;&#160;0x00000004U</td></tr>
<tr class="memdesc:ga88489f11e8c766bd4ba2c725087b16fc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Intr enable (in timer mode)  <a href="group___overview.html#ga88489f11e8c766bd4ba2c725087b16fc">More...</a><br/></td></tr>
<tr class="separator:ga88489f11e8c766bd4ba2c725087b16fc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3432c3b19bc44d4283ec4520b6e347d2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga3432c3b19bc44d4283ec4520b6e347d2">XSCUWDT_CONTROL_AUTO_RELOAD_MASK</a>&#160;&#160;&#160;0x00000002U</td></tr>
<tr class="memdesc:ga3432c3b19bc44d4283ec4520b6e347d2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Auto-reload (in timer mode)  <a href="group___overview.html#ga3432c3b19bc44d4283ec4520b6e347d2">More...</a><br/></td></tr>
<tr class="separator:ga3432c3b19bc44d4283ec4520b6e347d2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafd4c1f9ff31d9c47028759d68d945a8c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gafd4c1f9ff31d9c47028759d68d945a8c">XSCUWDT_CONTROL_WD_ENABLE_MASK</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:gafd4c1f9ff31d9c47028759d68d945a8c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Watchdog enable.  <a href="group___overview.html#gafd4c1f9ff31d9c47028759d68d945a8c">More...</a><br/></td></tr>
<tr class="separator:gafd4c1f9ff31d9c47028759d68d945a8c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Interrupt Status register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register indicates the Counter register has reached zero in Counter mode. </p>
</div></td></tr>
<tr class="memitem:ga48a52ba61af3b86522de83206703b0cf"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga48a52ba61af3b86522de83206703b0cf">XSCUWDT_ISR_EVENT_FLAG_MASK</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:ga48a52ba61af3b86522de83206703b0cf"><td class="mdescLeft">&#160;</td><td class="mdescRight">Event flag.  <a href="group___overview.html#ga48a52ba61af3b86522de83206703b0cf">More...</a><br/></td></tr>
<tr class="separator:ga48a52ba61af3b86522de83206703b0cf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Reset Status register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register indicates the Counter register has reached zero in Watchdog mode and a reset request is sent. </p>
</div></td></tr>
<tr class="memitem:ga09ce6fd05a79f896111beab252e792f5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga09ce6fd05a79f896111beab252e792f5">XSCUWDT_RST_STS_RESET_FLAG_MASK</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:ga09ce6fd05a79f896111beab252e792f5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Time out occurred.  <a href="group___overview.html#ga09ce6fd05a79f896111beab252e792f5">More...</a><br/></td></tr>
<tr class="separator:ga09ce6fd05a79f896111beab252e792f5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Disable register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register is used to switch from watchdog mode to timer mode.</p>
<p>The software must write 0x12345678 and 0x87654321 successively to the Watchdog Disable Register so that the watchdog mode bit in the Watchdog Control Register is set to zero. </p>
</div></td></tr>
<tr class="memitem:gaafdd114ae5e1835ff15037e617464de2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#gaafdd114ae5e1835ff15037e617464de2">XSCUWDT_DISABLE_VALUE1</a>&#160;&#160;&#160;0x12345678U</td></tr>
<tr class="memdesc:gaafdd114ae5e1835ff15037e617464de2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Watchdog mode disable value 1.  <a href="group___overview.html#gaafdd114ae5e1835ff15037e617464de2">More...</a><br/></td></tr>
<tr class="separator:gaafdd114ae5e1835ff15037e617464de2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3637e7d6bc621bbe36942a1bc9543f2f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___overview.html#ga3637e7d6bc621bbe36942a1bc9543f2f">XSCUWDT_DISABLE_VALUE2</a>&#160;&#160;&#160;0x87654321U</td></tr>
<tr class="memdesc:ga3637e7d6bc621bbe36942a1bc9543f2f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Watchdog mode disable value 2.  <a href="group___overview.html#ga3637e7d6bc621bbe36942a1bc9543f2f">More...</a><br/></td></tr>
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